sustechvhdl
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Lecture Documents:

  • 1. Introduction
  • 2. Data Objects and Operands
  • 3. Concurrent statement
  • 4. Sequential statement
  • 5. Modeling Structure
  • 6. Modeling at the RT level
  • 7. Modeling at the FSMD level
  • 8. Parameterized Design
  • 9. Pipelined design
  • 10. Subprograms, packages and libraries

Lab Documents:

  • 1. Task 1: Behavior Simulation of Full Adder (Week 2)
  • 2. Task 2: Behavior Simulation of Process (Week 3)
  • 3. Task 3: Implement your First Design – 1Hz 3-digit decade Counter (Week 5)
  • 4. Task 4: FSM and FSMD (Week 6)
  • 5. Task 5: Design Multipliers (Week 7)
  • 6. Task 6: Seven-Segment Display (Week 8)
  • 7. Task 7 Stepper Motor (week 9)
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