3. Task 3: Implement your First Design – 1Hz 3-digit decade Counter (Week 5)

Table of Contents

• Task 3: Implement your First Design – 1Hz 3-digit decade Counter (Week 5)
  • Knowledge Points

• Objective: Understand the modeling based on the hierarchical structure, the two segment coding style for the design of a sequential circuit, and implement the design on the FPGA board.

3.1. Knowledge Points

• Concurrent Statements

  • Conditional signal assignment statement, p78-81

• Sequential Statements

  • If statement, p105-111

• Data Type

  • Signed, Unsigned, p160-166

• Modeling Structure

  • Component Declaration & Component instantiation, p122-136
  • Configuration p137-141

• Synthesize memory device

  • latch, p182-185
  • flip-flop, p186-191

• Template for sequential circuit

  • two-segment coding style, p192-196

• Counter

• Testbench for sequential circuits

  • system clock, p206-207
  • system reset, p208-209
  • stimulus generation, p210-211