EE332 Digital System Design

Dr. Yu Yajun

Associate Professor, Department of Electrical and Electronic Engineering

Southern University of Science and Technology

Office: S236, South Tower, Engineering Building

Phone: 8801 8557

Email: yuyj@sustech.edu.cn

Text Book

P.P. Chu, RTL hardware design using VHDL, John Wiley & Sons, 2006.

Reference Book

• 19. Yalamanchili, VHDL: A Starter ‘ s Guide, Prentice Hall, 2005
• Charles H. Roth, Jr. and Lizy Kurian John: Digital Systems Design with VHDL, Publishing house of electronics Industry

Lecture Documents:

• 1. Introduction
  • 1.1. Digital system design
  • 1.2. What is VHDL
  • 1.3. Basic VHDL concept
• 2. Data Objects and Operands
  • 2.1. Data objects
  • 2.2. Data types
  • 2.3. Operators
  • 2.4. Lexical elements
• 3. Concurrent statement
  • 3.1. Simple CSA
  • 3.2. Conditional signal assignment
  • 3.3. Selected signal assignment
  • 3.4. Understanding delays
• 4. Sequential statement
  • 4.1. The process construct
  • 4.2. Sequential statements
  • 4.3. More on process
• 5. Modeling Structure
  • 5.1. Component
  • 5.2. Configuration
  • 5.3. Modeling a test bench
• 6. Modeling at the RT level
  • 6.1. Combinational circuit
  • 6.2. Sequential circuit
  • 6.3. Netlist of RTL components
  • 6.4. Test benches for sequential system
• 7. Modeling at the FSMD level
  • 7.1. Moore machine
  • 7.2. Mealy machine
  • 7.3. An FSM with a datapath (FSMD)
• 8. Parameterized Design
  • 8.1. Generics
  • 8.2. Array attribute
  • 8.3. Unconstrained Array
  • 8.4. Comparison
  • 8.5. Generate Statement
  • 8.6. Comparison
  • 8.7. For Loop Statement
  • 8.8. Comparison
• 9. Pipelined design
  • 9.1. Delay and throughput
  • 9.2. Overview on pipelined design
  • 9.3. Adding pipeline to a combinational circuit
• 10. Subprograms, packages and libraries
  • 10.1. Functions
  • 10.2. Package
  • 10.3. Design libraries

Lab Documents:

• 1. Task 1: Behavior Simulation of Full Adder (Week 2)
  • 1.1. Knowledge Points
• 2. Task 2: Behavior Simulation of Process (Week 3)
  • 2.1. Knowledge Points
  • 2.2. Example: Signal assignment with process
• 3. Task 3: Implement your First Design – 1Hz 3-digit decade Counter (Week 5)
  • 3.1. Knowledge Points
• 4. Task 4: FSM and FSMD (Week 6)
  • 4.1. Knowledge Points
  • 4.2. Sequential Recognizer
  • 4.3. ASMC for the Fibonacci Function
• 5. Task 5: Design Multipliers (Week 7)
  • 5.1. Knowledge Points
• 6. Task 6: Seven-Segment Display (Week 8)
  • 6.1. Knowledge Points Revisited
  • 6.2. New
  • 6.3. Understand the 7-Seg LED Display
• 7. Task 7 Stepper Motor (week 9)
  • 7.1. Knowledge Points Revisited